As DC-DC converters are scaled to the next generation of power converter products, there is a need to increase the switching frequency to reduce the size of the external passive components such as inductors while maintaining low power dissipation in its integrated power field effect transistors (FETs), such as LDMOS devices. In an LDMOS device, the drain is laterally arranged to allow current to laterally flow, and a drift region is interposed between the channel and the drain to provide a high drain to source breakdown voltage. This involves reducing the switching parasitics Qgate and Cdrain of the power FET while the ON-state resistance is also reduced.
Qgate is the charge required to turn ON the power FET gate during a switching transition in which the drain goes essentially between the power supply rails. Qgate causes (1) a power loss because this switching charge is not recovered during the switching process and (2) degraded area utilization because the circuitry needed to drive the gate of a large area power FET may occupy a significant fraction of the die area. Cdrain is the drain capacitance, which dictates how much charge is lost to switching per switching transition. RSP is the area-normalized ON-state resistance of the power FET. Conventionally, a new integrated power (e.g., linear BiCMOS (LBC)) technology will reduce the RSP so that the total ON resistance of a power switch may be attained at a reduced die area, hence reducing the product cost.